K7 (Athlon) SMP: What the future holds

by William Henning
Editor, CPUReview
Copyright July 12, 1999
ALL RIGHTS RESERVED

Introduction

Speculation and leaked benchmarks abound about AMD's upcoming Athlon (K7) processor [Editor: We tried to squeeze some information out of AMD in this interview; but they are very tight-lipped] and the latest tidbit of news comes from HotRail Inc.; a San Jose California core-logic start-up.

[Editor: links to HotRail and some references are at the end of this article.]

Their claim to fame is a "point-to-point switched fabric architecture"; basically a gigantic crossbar switch for processors, memory and peripherals that they call "Simultaneous Switched Matrix (tm)" abbreviated as SSM.

In case you are not familiar with such technology it is essentially a "router" for signals between processors and memory. Just like Ethernet switches it tries to implement a point-to-point link between the devices.

HotRail's site describes their SSM device as being appropriate for SMP (Symmetric Multi-Processor) systems with up to eight processors; they document their devices as having up to fourteen ports (for processors, memory and peripherals) with each port providing up to 3.2Gb/sec bandwidth.

The idea is:

• CPU#1 could retrieve information from memory port #1 while
• CPU#2 was writing to memory port #3 while
• an I/O controller is writing to memory port #3 from I/O port 1

And all of these devices can communicate over the SSM without excessive delays introduced due to arbitration (and cache coherency checks).

This is an excellent idea; and similar ideas have been used in super-computers to increase performance.

NEXT: The Problem

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