. . . are you sick of it yet? NOT! :) So yeah, if you haven't heard it, Intel has already announced its pricecut on most of the PIII and Celeron chips, as reported here by EB News (Hi Mark!). Summary on the new prices:

• PIII-800: -24% to $647
• PIII-750: -29% to $530
• PIII-733: -26% to $417
• PIII-700: -25% to $337
• PIII-650: -25% to $316
• PIII-600: -24% to $241
• PIII-550: -20% to $193
• PIII-533: -10% to $193
• Celeron-533: -24% to $127
• Celeron-500: -27% to $93
• Celeron-466: -18% to $73
• Xeon-800: -23% to $697
• Xeon-733: -22% to $505
• Xeon-667: -15% to $425

EB News reports that Nanya Technology, one of the big Taiwanese memory makers, is going to sample 256-Mbit and 128-Mbit DDR SDRAM is Q3 and Q4 2000 respectively. According to idiot, they are the first Taiwanese company to openly put out a roadmap for ramping up DDR DRAMs. Thanks Idiot!

Lucky boy JonHou over at FullOn3D was lucky enough to score an interview with VIA's Donald Eubank about the Cyrix III, check it out here . Jon, thanks for the link ;).

I am stunned, I am shocked, how is this possible ?

Ok, first of all, the our latest article is correct! The ALU's of the Willamette do not work at a real 3 GHz. BUT!

Got this e-mail from a very capable person:

While it appears that your understanding of double-pumping is mostly correct, the words "no 0.18um process... is able to produce units that switch at [3GHz]" - are wrong. If you are able to double pump a unit at 1.5GHz, then you can single pump it at 3GHz. In order to complete the 2 ALU operations in a single cycle at 1.5GHz, the logic must be able to fast enough to be clocked at 3GHz. The important thing about double-pumping is that it saves chip area. You use the same wires and logic to do two operations which, if done in parallel, would take twice as much area. It's a win from a designer's perspective since smaller chips are faster and lower power. It's mostly a non-issue from a end-user's perspective though.

According to this EETimes article, an organization known as OpenCores has developed a freely available RISC CPU core known as the OpenRISC 1000. Users will be able to download VHDL files as well as a C compiler from the site shortly.

This is somewhat similar to what Sun has done with SPARC, however, OpenRISC has very few, if any, legal strings attached. Individuals could produce and sell entire systems based around OpenRISC (though the core is still very simplistic at this point in time).

"I studied most of the RISC architectures that exist today and developed my own list of the most common and useful instructions. It's closest to the DLX or early MIPS architecture. It's a very basic 32-bit RISC with a load-store architecture and no floating-point capability at the moment," Lampret said. (The DLX processor is a RISC machine described by the pioneers of RISC, John Hennessy and David Patterson, in their book Computer Architecture: A Quantitative Approach (Morgan Kaufmann Publishers Inc.).

Lampret said he has settled on a mixed 16- and 32-bit instruction format. Although he has not pursued 16-bit format instructions or 16-to-32-bit instruction format translation (used in ARM's Thumb and considered good for embedded applications because it improves code density), Lampret said OpenRISC code is still compact compared with that of many other processors.

"I compiled the same code for X86, Sparc, MIPS and Alpha, and they were all bigger compiled programs," he said.

The register file architecture is similar to that of the Sparc, Lampret said. "It makes sense to have register windows. At the moment we have thirty-two, 32-bit registers, but that could change with different implementations."

PC Watch Japan has more coverage on Cyrix III, and more importantly, its successors Samuel and Matthew. Unfortunately I can only extract a few bits out from the report since it's in Japanese: Samuel is based on Winchip-4, and as I reported days ago, there will be two versions available. Sam II will have 256k L2 on-die cache and will debut in H1 2001; Sam I will have no L2 but less power-consuming and will be out by H2 2000. Also, VIA's answer to Intel's Timna is called Matthew, and info on Matthew remains sketchy. If I read it correctly, Matt will support DDR-SDRAM. As for integrated chipset, VIA is slated to introduce Apollo PM (ProMedia)-266 chipset with integrated Savage2000 and DDR-SDRAM in 2001.

Maybe it's because of Cebit, or maybe it's the lawsuits from Intel, but lately there has been a surge in number of VIA Apollo Pro 133A based motherboards in the market. Here are some reviews on the web of some of those motherboards: First, Anand has a round-up on 12 of those boards . Notice the unusually huge difference in performance among the boards. Also note the mention of the upcoming dual-cpu Tyan board based on the APP-133A. Next, Lost Circuits has a nicely detailed review on Shuttle AV64 . And finally, folks over at iXBT seem to be quite impressed with Chaintech's 6ATA4.

I think you going to find our our last article an interesting read. While visiting CEBIT, we gathered a ton of info about Intel's, AMD and VIA's future CPU's. Maybe this article can end some of the confusion...enjoy!

Our RC5-team is simply amazing...We break record after record. Not only did we enter the top 100 (Yep, Mark we noticed it too ; ), we are currently cruising at a >300.000 kkey/s speed, which result in no less than 100.000 block per day! Who would have imagined that we would be so strong now? just a few months ago, we cracked only 40.000 blocks per day.

So why wait? join a team that wants more!

Thanks to Idiot for informing me that 3dnow.org has published some notes from CeBIT. Armin's notes indicate overall that the Athlon platform seems to be shaping up with news of 950 MHz Athlon samples being shipped to OEMs and more motherboards from major manufacturers.

What probably stands out the most, however, is a picture of AMD's upcoming low-cost, socketed Spitfire CPU. Hopefully this is a positive sign we will indeed see a release of the Spitfire in May.

Our own Johan De Gelas also took a trip out to CeBIT, so you can expect some notes from us as well shortly.

Andreas Stiller, CPU Grandmaster, has written an excellent (what else did you expect ?) article about Intel's new Willamette. Especially interesting are the diagrams, like this one which gives a very good overview of the Willamette's micro-architecture.

No I-L1-cache, the trace cache is fed from the L2-cache. While the integer ALU's can crunch 4 integer micro ops per clock cycle, the trace cache can only make sure that a max. of 3 micro ops can be ready each clockcycle. Is it me or is the backend of the Willamette strong while the front end (fetching/decoding) is not wide enough ? Feel free to comment at our tech forum .

C't has tested the Cyrix III rather extensively, as you can read here . And unfortunately the Cyrix III 400 MHz (3x133 MHz) seems to be rather slow , compared to the Celeron 400 and K6-III 400. When I look at these scores (much more here )

benchmark	Cyrix 400	Celeron 400	K6-3 400
Quake 3	25.6	40.6	42.6
Expendable	20.4	34.4	30.8
Povray	169	255	229
Excel	71	76	89
Sysmark office	70	77	94

Where is that pipelined FPU ? I am starting to doubt if the Cyrix III really has one. Or is the 3DNow! unit the only one that is really pipelined ? The 3DNow! unit seems weak as we notice that the Quake 3 scores are low too.

We hope to test one ourselves too, but if I don't think VIA should label the Cyrix III 400 MHz as PR-500.

Thanks to Idiot for uncovering several Intel patents relating to the company's upcoming Willamette core.

• Method and apparatus for topology dependent slew rate control
• High gain pulse generator circuit with clock gating
• Fast fully associative translation lookaside buffer

Rise Technology, makers of the relatively short lived (on the desktop market) mP6 x86 processor, and STMicro have joined forces to produce a low-cost, low-power x86 core for general use in Internet appliances.

“Customers told ST they wanted a low-power X86 [core], that it had to be high-performance and at least Pentium class,” said David Lin, chairman and chief executive of Rise, Santa Clara, Calif. ST approached Rise after having apparently declined to partner with other companies, according to Lin.

Rise's mP6 and ST's STPC are unable to match the clock speed of processors from Intel Corp. and Advanced Micro Devices Inc. So Rise ended up late last year following ST into the embedded market for Internet appliances, as it discovered that set-top-box and thin-client OEMs were interested in the mP6's low power consumption.

Thanks to Al for mailing me about ATI's new S1-370 TL chipset (NorthBridge to be more specific) for Slot 1/Socket 370 systems. The chipset, like the i810e and other "value" chipsets, is targetted towards the low-cost PC sector, sporting features like integrated video. Unlike other low cost chipsets with integrated video, however, this one supports hardware 3D transforms and lighting (T&L). The graphics components were aquired from ArtX Inc.

Among the many amazing features of the ATI's S1-370 TL chipset is its support for transform and lighting technology, usually reserved for high-end graphics subsystems and add-in boards. T&L is one of the major elements required for next generation game titles and other applications to provide totally immersive and realistic environments with life-like characters that look and move like human figures.

With a through-put of 12.5 million polygons per second, four pixels per clock and greater than 330 million textured pixels/sec, ATI's S1-370 TL chipset delivers fast and realistic game performance. Major 3D features include accelerated floating point geometry; texture co-ordinate transformation clipping; perspective projection; accelerated specular, diffuse and ambient lighting; perspective-correct trilinear-filtered MIP-mapped textures; alpha blending; exponential pixel fog; depth and stencil buffering and anti-aliasing.

ATI's S1-370 TL outperforms Intel i810e.

Thanks to Palm, who pointed me to this page which talks about a watercooling that can be easily mounted on any sort of CPU. A Slot one version is ready now, a Socket 7, socket 370 and slot A will be announced soon.